As a method of producing an SOI wafer, there is known a method to produce a bonded SOI wafer by bonding two silicon single crystal wafers, that is, a base wafer to be a base substrate and a bond wafer to be formed with an SOI layer, through a silicon oxide film. As steps of producing such a bonded wafer, for example, there is known a method to form an oxide film on a surface of at least one of two wafers to bring them into contact closely and mutually without foreign materials on the bonded surface, and thereafter to subject them to a heat treatment at a temperature of about 200-1200° C. to enhance bonding strength thereof (see, Japanese Patent Publication (Kokoku) No. 5-46086).
A bonded wafer of which the bonding strength is enhanced by the heat treatment as described above can be subjected to subsequent grinding and polishing process. Therefore, an SOI layer to be formed with semiconductor devices can be formed by thinning the bond wafer to a desired thickness by grinding and polishing. However, when thinning by polishing is performed to the ground surface, if stock removal is set much, there is an advantage that small micro-roughness of the polished surface is improved, however there is a problem that uniformity of film thickness of the SOI layer in the whole of the wafer is degraded. Therefore, settable stock removal has an upper limit.
Accordingly, as a method of improving micro-roughness without degrading uniformity of film thickness, there is a high temperature heat treatment at 1000° C. or more in a non-oxidizing atmosphere. The treatment has become an effective method for improving the micro-roughness.
Moreover, recently as a technology for producing a ultra thin SOI wafer having an SOI layer of thickness of 0.1 μm or less with good uniformity of film thickness, an ion implantation delamination method (which is also referred to as a smart cut (a registered trademark) method) has been noticed (see, Japanese Patent No. 3048201).
The ion implantation delamination method is a technology of, for example, forming an oxide film on a surface of at least one of two wafers, therewith implanting at least one of hydrogen ions and rare gas ions from a surface of a bond wafer to form a micro bubble layer (an inclusion layer) inside the bond wafer such as near the surface thereof, thereafter bringing the bond wafer into contact closely with a base wafer through an oxide film on the ion-implanted surface side thereof, thereafter performing a heat treatment (a delaminating heat treatment) to delaminate the bond wafer thin-filmily so that the micro bubble layer is a cleaved surface (a delaminating plane), and further performing a heat treatment (a bonding heat treatment) to bond two silicon wafers tightly to provide an SOI wafer.
The surface (the delaminated surface) of the SOI wafer produced as described above becomes comparatively good mirror surface. However further polishing referred to as “touch polishing” in which stock removal is very small, 100 nm or less, is performed so that the SOI wafer has surface roughness equal to a general mirror-polished wafer.
Moreover, there is known a technology that a high temperature heat treatment in an atmosphere of hydrogen or Ar is performed instead of or along with the touch polishing to reduce surface roughness of the SOI layer and crystal defects with maintaining uniformity of film thickness of the SOI layer immediately after the delamination (Japanese Patent Laid-open (Kokai) No. 11-307472).
If the above-described ion implantation delamination method is used, an SOI wafer having very high uniformity of film thickness of an SOI layer can be comparatively easily obtained, and furthermore there is an advantage that material can be effectively usable because the other delaminated wafer can be recycled. Moreover, this method can be used in the case that when producing a bonded wafer, silicon wafers are mutually bonded directly without being through an oxide film. As well as bonding silicon wafers, the method can be used in the case that an SOI wafer is produced by implanting ions into a silicon wafer and bonding the silicon wafer to an insulating base wafer such as quartz, silicon carbide, alumina, or diamond which are different from a silicon wafer in coefficient of expansion.
There is an MIS (Metal/Insulator/Silicon) type transistor, in a kind of devices formed in an SOI layer of an SOI wafer produced as described above. With respect to a gate insulator film thereof, high performance electrical characteristics such as a low leakage current characteristic, low interface trap density, and high carrier injection resistance, and high reliability are required. As a technology forming a gate insulator film (mainly a silicon oxide film) meeting these requirements, a thermal oxidation technology has been conventionally used that a heat treatment is performed at 800° C. or more by using oxygen molecules or water molecules.
By using the thermal oxidation technology, a silicon oxide film having good characteristics of oxide film/silicon interface, a breakdown voltage characteristic of the oxide film, and a low leakage current characteristic can be conventionally obtained in the case that a silicon wafer having a plain orientation of {100} or a silicon wafer having a plain orientation angled approximately at 4 degrees from {100}. This is caused because interface trap density of a gate oxide film formed in a {100} plane is low compared to a gate oxide film formed in other crystal plane. Namely, a silicon oxide film formed in a silicon wafer having a plain orientation other than {100} by using a thermal oxidation technology has a high interface trap density of oxide film/silicon interface, a bad breakdown voltage characteristic of the oxide film, and a bad leakage current characteristic. Thus, the oxide film is inferior in electrical characteristics.
Therefore as a silicon wafer formed with MIS type semiconductor devices represented by so-called MOS (Metal/Oxide/Silicon) type transistors, an wafer having a plain orientation of {100} or an wafer having a plain orientation angled approximately at 4 degrees from {100}, has been conventionally used.
However, in recent years, a technique has been developed that a good-quality oxide insulator film is formed regardless of a plain orientation of a silicon wafer surface by using Kr/O2 plasma (see, for example, Saito et al., “Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide”, 2000 Symposium on VLSI Technology, Honolulu, Hi., Jun. 13th-15th, 2000.). Namely, if the technique is used that a good-quality oxide insulator film regardless of a plain orientation of a silicon wafer is formed, it is not necessary to limit a plain orientation of a silicon wafer for forming MOS type semiconductor devices to {100}. A silicon wafer having a plain orientation having most suitable characteristics for any purpose is possibly used.
For example, it has been revealed that a carrier mobility in a channel direction of an MOSFET (MOS Field Effect Transistor) become twice or more in a specific direction of an wafer having a plain orientation of {110} for some cases, and that as a result, a current value between drain and source is increased.
Therefore, if by using a silicon single crystal wafer in which a plain orientation is a {110} plane as an wafer for fabricating MOS type devices, a gate insulator film is formed by the technique of forming an insulator film of good-quality regardless of a plain orientation as described above, there is possibility to fabricate MOS devices having an innovatively excellent characteristics such as high speed devices for which high carrier mobility is utilized.
Moreover, because the advantage of a {110} plane such as high carrier mobility as described above is the same in an SOI wafer, and originally an SOI wafer has most suitable characteristics for forming high speed and high performance devices, an SOI wafer having a plain orientation of an SOI layer of {110} has been demanded more and more in recent years.